This object is achieved for digital timer by mean of a pulse generator, circuits of a number of binary reducer or dividers each associated with one resistor, all of these divider counting their extant "1"state and effecting a digital-analogue conversion, a magnet actuated by mean of a comparator when the potential formed at the resistor reache a predetermined value, and the resistor associated with the binary divider all having the same resistance,so that at those times corresponding to the powers of 2 (standard timing series), there are potentials of such values as correspond to the logarithm of the time (interval) being formed.
This voltage counting always increases logarithmically at the reference times of the time (interval) being formed. While these summed potentials assume other values between the reference times, these differentvalues however are always less than the potential occurring at the next reference time. If, however, only the reference times are being considered, then the rise in potential indeed takes place solely logarithmically. An enevelope on or above thepotential peaks therefore also shows a purely logarithmic curve.
In order to form all the reference timing from 1 second to 1/2,000 second = 12 timings, 12 binary dividers are required in the circuit. The provides circuitry requiring only part of these(twelve) binary dividers, the pulse generator feeding these binary dividers after a certain time being lowered in frequency and the binary dividers that are present becoming doubly effective. Not only does this embodiment save binary dividers proper,but also a corresponding number of resistors.
Furthermore, a digitally operating timer already has been proposed, which comprises a memory and a decoder which are hooked up to a set of binary dividers or reducers, so that a signal is emitted upon thedesired time interval. The first of these timers, however, requires an additional series of binary dividers or reducers, which set must be controlled during the timing process and the second timer requires a memory and hence an appreciable amount ofcomponents. Furthermore, as regards both of these digital timers, the desired time interval must be known before triggering.
The novel timer is so constructed by means of additional resistors and logic gate circuits that intermediate timings between the individual reference timings are easily obtained. Thisrepresents another advantage of the digital timer the with respect to the state of the art, the latter’s timers being unsuitable to form intermediate timings.
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